Host processor systems may store and retrieve data using a storage device containing a plurality of host interface units (host adapters), disk drives, and disk interface units (disk adapters). Such storage devices are provided, for example, by EMC Corporation of Hopkinton, Mass., and disclosed in U.S. Pat. No. 5,206,939 to Yanai et al., U.S. Pat. No. 5,778,394 to Galtzur et al., U.S. Pat. No. 5,845,147 to Vishlitzky et al., and U.S. Pat. No. 5,857,208 to Ofek. The host systems access the storage device through a plurality of channels provided therewith. Host systems provide data and access control information through the channels of the storage device and the storage device provides data to the host systems also through the channels. The host systems do not address the disk drives of the storage device directly, but rather, access what appears to the host systems as a plurality of logical volumes. The logical volumes may or may not correspond to the actual disk drives.
A cyclic redundancy check (CRC) is an error-detecting code. A CRC-enabled sending/storing device calculates a short, fixed-length binary sequence, known as the CRC code or just CRC, for each block of data and sends or stores the CRC with the data block. When the data block is read or received, the reading/receiving device repeats the calculation; if the new CRC does not match the one calculated earlier, or otherwise indicates an inconsistency, then the data block contains a data error and the reading/receiving device may take corrective action such as rereading or requesting the data block be sent again. The CRC may be 16-bit protection word provided to ensure data integrity per data block in data interchange format (DIF). The computation of the CRC may resemble a long division operation in which the quotient is discarded and the remainder becomes the result, although the arithmetic used is carry-less arithmetic of a finite field. For a general discussion of CRC computations, see “A Tutorial on CRC Computations,” IEEE Micro, Vol. 8, Issue 4, 1988, pp. 62-75, which is incorporated herein by reference.
In a storage device, a CPU local transfer mode, including I/O and XOR operations, may be provided to allow the CPU to move data between global memory and local control storage spaces for global memory stored locally to the CPU. For I/O data in DIF format, the CPU may check each data block's CRC to verify its integrity. With known CRC computation algorithms, each data block (512 byte) may require at least approximately 350 ns for the CPU to compute the DIF CRC (using, for example, an Intel Core-2 microprocessor). In comparison, the CPU needs only approximately 30 ns to complete a simple data copy (without CRC verification). Thus, the DIF CRC computation for verification may slow down local data transfer by a factor of 10. For example, for a 64K Read-Hit benchmark, the CRC computing may consume 60% (or even higher) of total CPU cycles. Generally, known CRC verification techniques may be unacceptably inefficient when implemented using software.
Accordingly, it would be desirable to provide a system that more efficiently verifies data block CRCs for error detecting and related operations.